Conventional data sampling circuits can capture a data input value in response to a clock signal (such as a rising or falling edge of a clock signal). One conventional data sampling circuit 700-A is shown in FIG. 7A. A data sampling circuit 700-A can be a D-type flip-flop (FF), latching a data value (Data) on a rising edge of clock signal (Clk). While such conventional sampling can provide adequate results at slower data speeds (i.e., less than 1 GHz), at higher speeds jitter, skew and pulse narrowing (which can occur from inter-symbol interference (ISI)) can result in incorrect sampling, leading to an erroneous output value (Dataout).
A single D-type FF sampling circuit, like that of FIG. 7A can suffer from metastability, particularly if set-up and hold times are violated. Another conventional data sampling circuit 700-B, shown in FIG. 7B, can be used to address metastability problems. Data sampling circuit 700-B can include D-type FFs 701-0 to -2 arranged in series with one another. FF 701-0 can sample a data value according to a clock signal (Clk). FF 701-1 can re-sample the output of FF 701-0 with a clock that is phase delayed by 45° with respect the clock signal (Clk). FF 701-2 can re-sample the output of FF 701-1 with a clock that is phase delayed by 90° with respect the clock signal (Clk). While data sampling circuit 700-B can address metastability problems, it can still yield erroneous values in response to jitter, skew and pulse narrowing.
Another conventional data sampling circuit 700-C is shown in FIG. 7C. Data sampling circuit 700-C can include a conventional D-type FF stage 701, followed by a decision feedback equalization (DFE) circuit 703, which can alter a sampling process based on a previously detected value. While DFE-type sampling circuit 700-C can provide high speed operations, and can remove effects of ISI, it can remain vulnerable to jitter and skew effects.
FIG. 7D shows a conventional transition detection circuit 700-D. Transition detection circuit can include serial connected D-type FFs 701-0/1, 701-2/3, and XOR gates 705-0/1. FFs 701-0/1 can be clocked by a clock signal (01k). An output of FF 701-0 can be provided as a first input to an XOR gate 705-0, while an output of FF 701-1 can be provided as a first input to XOR gate 705-1. FFs 701-2/3 can be clocked by a clock signal that is phase shifted by 180° with respect to signal Clk. Outputs of XOR gates 705-0/1 can indicate the location of a data transition. It is noted that data transition detection circuit 700-D is not used for data capture.